1. Field of the Invention
The present invention relates to a technique to control a processing of data in a configuration where a plurality of data processings are performed concurrently and in parallel.
2. Description of the Background Art
When a CPU (Central Processing Unit) executes a program, generally, a series of operations combining a plurality of simple operations such as (1) fetch of an instruction, (2) decoding of the instruction and (3) execution of the instruction is repeated. For example, a data transfer processing is performed by repeating such a series of processings.
Now, a discussion will be made on a processing performed by a CPU inside a semiconductor memory device when the memory device receives data in a unit of sector from a host computer (hereinafter referred to as xe2x80x9chostxe2x80x9d). FIG. 7 is a timing chart showing a case where operations or process steps ST1 to ST4 are executed on data D1 and then the process steps ST1 to ST4 are executed on the next data D2. As shown in FIG. 7, the CPU in the memory device repeats a series of operations, i.e., (A) fetching data and storing it in a sector buffer inside the memory device (step ST1), (B) adding an error correcting code (ECC) to the received data (step ST2), (C) writing the data into a flash memory inside the memory device (step ST3) and (D) checking a write result (step ST4). The priorities of operations which the CPU executes are the steps ST4, ST3, ST2 and ST1 from higher to lower.
One of effective methods of executing a series of operations consisting of the steps ST1 to ST4 at higher speed is pipelining of the data processing. Specifically, respective circuits for the steps ST1 to ST4 are operated independently and in parallel, to improve operation efficiency. Such a pipelined processing is shown in a timing chart of FIG. 8. As shown in FIG. 8, a circuit used for the data fetch operation ST1 consecutively performs the operation ST1 on a plurality of data D1 to D5. As can be seen from comparison between FIGS. 7 and 8, this pipelined processing of FIG. 8 can achieve a throughput twice and half as much as that of the processing of FIG. 7 in the same time period from the time t0 to the time t8.
While the data transfer processing is performed, the CPU always controls the states of the sector buffers used for the data transfer and the states of all the operations during execution. Specifically, the CPU checks whether or not each circuit completes its operation on data and is available for the operation on the next data, and if the circuit is available, the CPU makes the circuit perform the operation on the next data. Further, in the data fetch operation ST1, the CPU performs a control so as to avoid a wrong order of readout of data from the host.
A more specific discussion will be made on the pipelined data transfer processing and the above control of data processing by the CPU. FIG. 9 is a schematic diagram of a conventional address space in a RAM (Random Access Memory) 12P used by the CPU. As shown in FIG. 9, the RAM 12P comprises a firmware processing region 13P for storing instructions or programs (generally termed firmware (F/W)) needed to operate the CPU and an operation region 14P (hereinafter referred to as xe2x80x9cwork bufferxe2x80x9d) for controlling a pipelined processing.
The work buffer 14P consists of the first to fourth work buffers 141P to 144P and the four work buffers 141P to 144P each store a current processing of predetermined data under execution. For example, at the time to in FIG. 8 (see the state S1), the CPU controls the circuit for the operation ST1 to execute the fetch operation ST1 on the data D1 while writing information indicating that the data D1 is being subjected to the operation ST1 into the first work buffer 141P. After that, at the time t1 (see the state S2), the CPU controls the circuit for the operation ST2 to execute the ECC addition operation ST2 on the data D1 stored in the sector buffer while writing information indicating that the data D1 is being subjected to the operation ST2 into the first work buffer 141P. On the other hand, at the same time t1, the CPU controls the circuit for the operation ST1 to execute the fetch operation ST1 on the data D2 while writing information indicating that the data D2 is being subjected to the operation ST1 into the second work buffer 142P, like the above-discussed state S1. Thus, the operations sequentially proceeds. The first work buffer 141P, for example, is used as a work buffer only for the data D1 until a series of operations ST1 to ST4 on the data D1 are completed.
At this time, as conventional access methods when the CPU uses the work buffers 141P to 144P, (a) a method in which absolute addresses AD141P, AD142P, AD143P and AD144P of the work buffers 141P, 142P, 143P and 144P, respectively, are designated by firmware or in a program, (b) a method in which the address AD141P of the work buffer 141P is used as a base address and the other work buffers 142P, 143P and 144P are designated by offset addresses, and the like are used.
The above addresses AD141P, AD142P, AD143P and AD144P are mapped to addresses P1P, P2P, P3P and P4P, respectively, in the address space of the CPU, and the CPU accesses the addresses P1P, P2P, P3P and P4P to access the above addresses AD141P, AD142P, AD143P and AD144P.
When the CPU performs the above-discussed processing control, generally, the loading of the CPU, in other words, the processing time increases. As a result, the speed of data processing or the performance of data transfer is deteriorated. This tendency becomes more pronounced as the number of data to be pipeline-processed increases. Since the above data processing control is needed when a plurality of data processings are performed in parallel, it is strongly desired that the CPU operates with higher efficiency while performing such a processing control. One of measures to meet such a requirement is to improve an access of the CPU to the work buffers. Specifically, both the conventional access methods (a) and (b) have the following problem.
Discussing in detail, in both the access methods (a) and (b), the CPU has to control the correspondence between the data D1 to D5 and the first to fourth work buffers 141P to 144P. For example, in FIG. 8, the data to be subjected to the operation ST4 to which the highest priority should be assigned by the CPU is changed from the data D1 to the data D2 when the state shifts from the state S4 from the time t3 till the time t4 to the state S5 from the time t4 till the time t5. At that time, with the change of the data to be subjected to the operation ST4, the work buffer to be accessed by the CPU in executing the operation ST4 is changed from the first work buffer 141P to the second work buffer 142P. Therefore, in both the conventional access methods (a) and (b), the CPU itself has to memory and control the addresses AD141P to AD144P of the work buffers to be accessed by the CPU in executing the operations ST1 to ST4.
Further, when the state shifts from the state S4 to the state S5, the first work buffer 141P used only for the data D1 is relieved (in an open state) and available to the next data D5. Specifically, the CPU always has to memory and control which one of the first to fourth work buffers 141P to 144P is available to the data fetch operation ST1.
Thus, in both the conventional access methods (a) and (b), the CPU has to control not only the data processing control but also the address of the work buffer to be accessed for the processing control and whether the work buffer is available or not.
One of control methods which could lighten the burden for controlling the address of the work buffer and whether available or not is as follows. Specifically, a possible method is to sequentially copy (move) the informations in the second to fourth work buffers 142P to 144P, such as copying the information in the second work buffer 142P to the relieved first work buffer 141P and then copying the information in the third work buffer 143P to the relieved second work buffer 142P and so on. According to this control method, unlike the access methods (a) and (b) in which the first to fourth work buffers 141P to 144P each correspond to the specified data, the work buffers 141P to 144P correspond to the priorities of the operations ST4 to ST1 in this order. Therefore, in executing the operation ST4, for example, the CPU always has only to access the first work buffer 141P. Further, in order to check if the work buffers are available, the CPU has only to access the fourth work buffer 144P. To copy the informations in all the work buffers 141P to 144P as above, however, it takes several tens xcexc sec for the CPU. Specifically, it is difficult to achieve the intended object of improving the operation efficiency of the CPU, in other words, to perform the data processing at higher speed.
The present invention is directed to a data processing control device. According to a first aspect of the present invention, the data processing control device comprises: a CPU for performing a control of a processing performed on each of a plurality of data which is sequentially processed through a plurality of process steps which can be concurrently performed, the control being made by using a plurality of first addresses which are different from one another and in correspondence with the plurality of process steps; a plurality of control memory units having a plurality of second addresses which are different from one another, for storing information on the plurality of data on a data-by-data basis; and an address conversion unit for associating the plurality of first addresses and the plurality of second addresses in an address correspondence which varies as the processing is shifted.
According to a second aspect of the present invention, in the data processing control device of the first aspect, the plurality of data are subjected to the same processing, and the plurality of first addresses circularly changes with respect to each of the second addresses as the processing is shifted.
According to third and fourth aspects of the present invention, in the data processing control device of the first and second aspects, the plurality of data include first data and second data, and as the processing is shifted from a state where the second data is processed in the process step whose priority is lower than the process step for processing the first data to a state where the second data is processed in the process step whose priority is higher than the process step for processing the first data, in the address correspondence, one of the first addresses associated with one of the second addresses with respect to the first data is interchanged with another one of the first addresses associated with another one of the second addresses with respect to the second data.
In the data processing control device of the first aspect, the first addresses correspond to the process steps of the data and are associated with the second addresses in the address correspondence which varies as the processing is shifted. Therefore, it is not necessary to move the contents stored in the control memory units as the processing is shifted. Moreover, the CPU can grasp the currently-performed processing in a desired process step by selecting one of the first addresses without controlling which data is processed in each of the process steps. Therefore, it is possible to reduce the loading and processing time needed to control the currently-performed processing as compared with the background-art device. At this time, a program which the CPU executes to control the processing become simpler and smaller than a background-art program. As a result, the operation efficiency of the CPU can be improved.
In the data processing control device of the second aspect, when a plurality of data are subjected to the same processing, if the processing order of the data does not change or differ by process steps, the correlation between the order of the first addresses and the order of the second addresses is not broken even if the first addresses are circularly changed. Therefore, the CPU can use an offset address with respect to one of the first addresses to access a desired control memory unit. At this time, since it is not necessary to write all the first addresses in a program executed by the CPU, the program can be easily made simpler and smaller.
In the data processing control device of the third and fourth aspects, even when it is changed in accordance with the currently-performed processing whether the process step for processing the first data is performed before or after the process step for processing the second data, by using the first addresses, it is possible to reliably control the currently-performed processing, in accordance with the process step.
An object of the present invention is to provide a data processing control device which allows an improvement in operation efficiency.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.